Integration of low k methyl silsesquioxane in a non-etchback/CMP process for 0.25 μm LSI device

Author

Jeong, H.D. ; Park, H.S. ; Shin, H.J. ; Kim, B.J. ; Kang, H.K. ; Lee, M.Y.

Author_Institution

R&D Center, Samsung Electron. Co., Yongin City, South Korea

fYear

1999

fDate

1999

Firstpage

190

Lastpage

192

Abstract

A nonetchback intermetal dielectric (IMD) process using cage-type methyl silsesquioxane (MSQ) is demonstrated for 0.25 μm LSI devices. The peeling problem of plasma enhanced TEOS (P-TEOS) SiO₂ on the MSQ during the chemical mechanical polishing (CMP) process is solved by using NH₃-N₂ plasma treatment. This adhesion improvement is due to the decrease in Si-CH₃ bonds and formation of Si-NH on the MSQ surface. Parasitic capacitance for MSQ is 28% lower than that for HDP-SiO₂. The via poisoning problem is greatly suppressed by NH₃-N₂ plasma treatment at the via

Keywords

adhesion; capacitance; chemical mechanical polishing; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; large scale integration; organic compounds; permittivity; plasma materials processing; 0.25 micron; CMP; LSI device; LSI devices; MSQ surface; NH₃-N₂; NH₃-N₂ plasma treatment; P-TEOS SiO₂ peeling; Si-NH; Si-NH formation; SiO₂; adhesion; cage-type methyl silsesquioxane; chemical mechanical polishing; low k methyl silsesquioxane; nonetchback IMD process; nonetchback intermetal dielectric process; nonetchback/CMP process; parasitic capacitance; plasma enhanced TEOS SiO₂ peeling; process integration; via poisoning; Adhesives; Large scale integration; Parasitic capacitance; Performance analysis; Plasma applications; Plasma chemistry; Plasma devices; Plasma measurements; Plugs; Surface treatment;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology, 1999. IEEE International Conference

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-5174-6

Type

conf

DOI

10.1109/IITC.1999.787118

Filename

787118