DocumentCode
3085750
Title
Integration of III-V nanowires on Si: From high-performance vertical FET to steep-slope switch
Author
Tomioka, Katsuhiro ; Yoshimura, Masashi ; Nakai, Eiji ; Ishizaka, Fumiya ; Fukui, T.
Author_Institution
Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
fYear
2013
fDate
9-11 Dec. 2013
Abstract
In this paper, we present recent progress in the integration of vertical III-V nanowire-channels on Si by selective-area epitaxy and demonstrations of high-performance III-V vertical surrounding-gate transistors with high-k dielectrics with an EOT of less than 1 nm, modulation doping technique, and challenges in steep subthreshold-slope switching using III-V nanowire/Si heterojunctions as building blocks for low power circuits.
Keywords
III-V semiconductors; elemental semiconductors; field effect transistors; nanowires; semiconductor heterojunctions; silicon; Si; high k dielectrics; high performance vertical FET; low power circuits; modulation doping technique; nanowire channels; selective area epitaxy; steep slope switch; steep subthreshold slope switching; vertical surrounding gate transistors; Heterojunctions; Indium gallium arsenide; Logic gates; Nanowires; Silicon; Switches; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/IEDM.2013.6724557
Filename
6724557
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