Evolutionary graph generation system with transmigration capability for arithmetic circuit design

Author

Homma, Noriyasu ; Aoki, Tukufumi ; Higuchi, Tutsuo

Author_Institution

Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

Volume

5

fYear

2001

fDate

2001

Firstpage

171

Abstract

This paper presents a novel graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. This paper also demonstrates that the evolution process of EGG can be accelerated by a simple operation, called “transmigration”, which is to import previously generated good solutions for creating the other solutions

Keywords

circuit CAD; circuit optimisation; digital arithmetic; evolutionary computation; graph theory; logic CAD; multiplying circuits; parallel architectures; EGG; arithmetic circuit design; evolutionary graph generation system; fast constant-coefficient multipliers; graph-based evolutionary optimization technique; parallel counter-tree architecture; transmigration capability; Acceleration; Algorithm design and analysis; Circuit synthesis; Digital arithmetic; Encoding; High level synthesis; Libraries; Logic circuits; Signal processing algorithms; Tree graphs;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922012

Filename

922012