DocumentCode
3086691
Title
Retention time optimization for eDRAM in 22nm tri-gate CMOS technology
Author
Yih Wang ; Arslan, Umut ; Bisnik, Nabhendra ; Brain, R. ; Ghosh, Sudip ; Hamzaoglu, Fatih ; Lindert, Nick ; Meterelliyoz, Mesut ; Park, Jongho ; Tomishima, Shigeki ; Zhang, Kai
Author_Institution
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
fYear
2013
fDate
9-11 Dec. 2013
Abstract
A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.
Keywords
CMOS integrated circuits; DRAM chips; low-power electronics; optimisation; system-on-chip; Gbit eDRAM; critical circuits; design cooptimization; eDRAM bitcell; high performance eDRAM technology; high-performance trigate CMOS SoC technology; low-power 22nm trigate CMOS SoC technology; noise reduction circuit techniques; retention time optimization; size 22 nm; temperature 95 C; Capacitance; Computer architecture; Microprocessors; Noise; Transistors; Voltage control; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/IEDM.2013.6724595
Filename
6724595
Link To Document