A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation

This paper starts with the introduction of the Synchronous Transfer Architecture (STA), a new variant of VLIW architecture which can be viewed as a version of Transport-Triggered Architectures (TTA). Since the quality of assembly code generated by traditional high-level language compiler for such architectures is not satisfactory, we propose a novel phase-coupled compiler, in which the instruction selection and register allocation are solved together by using a two-step register allocator. According to our studies, this approach can reduce both execution time and size of the generated code by about 40%-60% in comparison to code assembled by conventional (phase-separated) compilers. Moreover, assembly code quality achieved by using two-step register allocation is comparable to the code quality obtained by a phase-coupled compiler backend based on Integer Linear Programming which requires much longer compilation time.