• DocumentCode
    3087100
  • Title

    Implicit test sequences compaction for decreasing test application cost

  • Author

    Bevacqua, R. ; Ferrandi, F. ; Fummi, F. ; Guerrazzi, L.

  • Author_Institution
    Dip. di Elettronica e Inf., Politecnico di Milano, Italy
  • fYear
    1996
  • fDate
    7-9 Oct 1996
  • Firstpage
    384
  • Lastpage
    389
  • Abstract
    Test pattern storage is an important problem affecting all Design for Testability (DfT) techniques based on scan-path. Test compaction is the key idea to reduce this problem, but in case of partial-scan test compaction would concern the concatenation and overlapping of test sequences instead of test vectors. Unfortunately, standard sequential TPGs do not show sufficient capabilities in test sequences compaction. Thus, the paper presents an innovative compaction strategy for test sequences based on implicit techniques. Preliminary results show that the use of the presented technique can sensibly reduce the amount of test patterns which mast be stored and applied
  • Keywords
    design for testability; logic CAD; logic testing; Design for Testability; compaction strategy; scan-path; test application cost; test compaction; test pattern storage; test sequences; test sequences compaction; Automata; Circuit faults; Circuit testing; Compaction; Costs; Design for testability; Fault detection; Fault diagnosis; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-8186-7554-3
  • Type

    conf

  • DOI
    10.1109/ICCD.1996.563583
  • Filename
    563583