Estimation of transient voltage fluctuations in the CMOS-based power distribution networks

Author

Tang, Kevin T. ; Friedman, Eby G.

Author_Institution

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA

Volume

5

fYear

2001

fDate

2001

Firstpage

463

Abstract

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. These transient IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. Circuit and layout-level design constraints are also discussed to manage the peak value of the transient IR voltage drops

Keywords

CMOS logic circuits; VLSI; delays; integrated circuit layout; power supply circuits; transients; CMOS logic gate; CMOS-based power distribution networks; delay uncertainty; layout-level design constraints; on-chip currents; peak value; power distribution network; propagation delay; transient IR voltage drops; transient voltage fluctuations; voltage changes; CMOS integrated circuits; CMOS logic circuits; Frequency; Logic gates; Network-on-a-chip; Power supplies; Power systems; Propagation delay; Uncertainty; Voltage fluctuations;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922085

Filename

922085