Performance predictions for speculative, synchronous, VLSI logic simulation

Author

Noble, Bradley L. ; Wade, J. Cris ; Chamberlain, Roger D.

Author_Institution

Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Edwardsville, IL, USA

fYear

2001

fDate

2001

Firstpage

56

Lastpage

64

Abstract

VLSI logic simulation is an application area in which execution time improvements can have direct economic benefits. Here, we investigate the use of parallel simulation techniques to improve the performance of VLSI logic simulation, including the often neglected issue of sensitivity to variations in the simulation workload. Performance predictions are presented for the use of speculative computation in synchronous discrete-event simulation of VLSI systems

Keywords

VLSI; circuit complexity; discrete event simulation; logic simulation; parallel programming; software performance evaluation; discrete-event simulation; execution time; parallel simulation; performance predictions; simulation workload sensitivity; speculative computation; synchronous VLSI logic simulation; Application specific integrated circuits; Circuit simulation; Computational modeling; Computer simulation; Discrete event simulation; Error correction; Hardware design languages; Logic; Predictive models; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation Symposium, 2001. Proceedings. 34th Annual

Conference_Location

Seattle, WA

ISSN

1080-241X

Print_ISBN

0-7695-1092-2

Type

conf

DOI

10.1109/SIMSYM.2001.922115

Filename

922115