A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application

Author

Ruan, Jian ; Lee, Chung Len

Author_Institution

Peking Univ., Peking

fYear

2008

fDate

23-25 Jan. 2008

Firstpage

99

Lastpage

102

Abstract

This paper presents a differential input, two-stage structure sample-hold-amplifier (SHA) for which each stage can be designed and adjusted separately to have a large input dynamic range and fast operation speed. The clock feed through and charge injection is eliminated. The implemented SHA with a 0.18 mum 1.8 V process shows that it can sample a 2.5 MHz signal at 40 MHz with a 63 dB SFDR and a -62 dB THD which is able to realize an ADC of 10 bit resolution.

Keywords

analogue-digital conversion; differential amplifiers; sample and hold circuits; analogue-digital conversion; differential input amplifier; frequency 2.5 MHz; frequency 40 MHz; pipelined ADC application; size 0.18 mum; two-stage sample-and-hold amplifier; voltage 1.8 V; Capacitance; Clocks; Coupling circuits; Differential amplifiers; Dynamic range; Electronic equipment testing; Linearity; Operational amplifiers; Sampling methods; Switches; Bootstrapped switch; Bottom-plate sampling; Pipelined ADC; Sample-and-hold amplifier; Two-stage structure;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on

Conference_Location

Hong Kong

Print_ISBN

978-0-7695-3110-6

Type

conf

DOI

10.1109/DELTA.2008.58

Filename

4459518