A fault hypothesis study on the TTP/C using VHDL-based and pin-level fault injection techniques

Fault injection techniques are frequently used for validating dependable systems. VHDL-based techniques are good resources that support fault injection with many advantages such as a high level of accessibility, controllability and precision. This paper presents the results obtained with a VHDL-based tool (VFIT) injecting single and multiple faults at pin-level in a TTP/C model. The study is focused on the fault hypothesis of a modelled communications protocol based on the Time-Triggered Architecture. Results are analysed and compared with the experiments carried out in the real prototyped system with a pin-level fault injection tool (AFIT). Conclusions strengthen the usability of VHDL-based fault injection tools and reveal technique weaknesses.