Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation

Author

Tan, Kah-Howe ; Leong, Wen Fung ; Kadam, Sameer ; Soderstrand, M.A. ; Johnson, Louis G.

Author_Institution

Sch. of Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK, USA

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

514

Abstract

Savings ranging from 36% to 53% in FPGA resources are achieved through a filter design program that simultaneously applies optimum scaling, careful selection of filter order and use of fixed-coefficient multipliers designed with CSD and/or DM techniques. The output of the program is a VHDL description of the optimized hardware that is suitable as input to the Synplify Pro computer program that generates highly optimized FPGA circuits for Xilinx and other FPGA´s

Keywords

circuit optimisation; digital filters; field programmable gate arrays; hardware description languages; high level synthesis; public domain software; CSD technique; DM technique; FPGA circuit optimization; Synplify Pro computer program; VHDL; Xilinx; filter design; fixed-coefficient multiplier; public-domain Matlab software; Adders; Circuits; Delta modulation; Digital filters; Field programmable gate arrays; Finite impulse response filter; Hardware; MATLAB; Signal design; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922287

Filename

922287