A bi-directional current-mode CMOS multiple valued logic memory circuit

Author

Current, K.W. ; Hurlston, M.E.

Author_Institution

Dept. of Electr. Eng., California Univ., Davis, CA, USA

fYear

1991

fDate

26-29 May 1991

Firstpage

196

Lastpage

202

Abstract

A bidirectional current-mode multiple-valued logic (MVL) latch circuit realized in a standard 2-μm polysilicon gate CMOS process is presented. The circuit accepts and quantizes a bidirectional input current during the setup clock phase and latches the quantized input during the hold clock phase. Characteristics of fully integrated prototypes realized on a CMOS test chip are presented. Using logical current increments of only 10 μA, the bidirectional current-mode MVL latch´s setup and hold time has been determined to total approximately 44 ns. The input/output propagation delay for transitions between adjacent states has been determined to be approximately 50 ns at these low current levels

Keywords

CMOS integrated circuits; integrated logic circuits; integrated memory circuits; many-valued logics; 10 muA; 2 micron; 2-μm polysilicon gate CMOS process; 44 ns; 50 ns; bi-directional current-mode CMOS multiple valued logic memory circuit; bidirectional current-mode MVL; input/output propagation delay; Adders; Arithmetic; Bidirectional control; CMOS logic circuits; CMOS memory circuits; CMOS technology; Clocks; Integrated circuit technology; Latches; Multivalued logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1991., Proceedings of the Twenty-First International Symposium on

Conference_Location

Victoria, BC

Print_ISBN

0-8186-2145-1

Type

conf

DOI

10.1109/ISMVL.1991.130729

Filename

130729