An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores

Author

Olivieri, Mauro ; Trifiletti, Alessandro

Author_Institution

Univ. of Roma La Sapienza, Italy

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

638

Abstract

Clock generator cores play an increasingly important role in the VLSI design of embedded microprocessors supporting specialized power management modes. We present a fully digital, standard-cell-based design of a specialized PLL architecture that can be recompiled on different cell libraries. On a 0.45 μm CMOS implementation, the circuit features a 16 ps jitter, 19.5-to-72 MHz frequency range with a 32 KHz input, and less than 50 clock cycles wakeup time

Keywords

CMOS digital integrated circuits; VLSI; cellular arrays; clocks; digital phase locked loops; embedded systems; microprocessor chips; 0.45 micron; 19.5 to 72 MHz; CMOS circuit; PLL architecture; VLSI design; all-digital clock generator firm-core; differential fine-tuned delay; embedded microprocessor; power management; reusable microprocessor core; standard cell; Circuits; Clocks; Distributed power generation; Energy management; Jitter; Microprocessors; Phase locked loops; Power generation; Software libraries; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922318

Filename

922318