New subthreshold concepts in 65nm CMOS technology

Author

Moradi, Farshad ; Wisland, Dag T. ; Mahmoodi, Hamid ; Peiravi, Ali ; Aunet, Snorre ; Cao, Tuan Vu

Author_Institution

Dept. of Inf., Univ. of Oslo, Oslo

fYear

2009

fDate

16-18 March 2009

Firstpage

162

Lastpage

166

Abstract

In this paper challenges observed in 65 nm technology for circuits utilizing subthreshold region operation are presented. Different circuits are analyzed and simulated for ultra low supply voltages to find the best topology for subthreshold operation. To support the theoretical discussions different topologies are analyzed and simulated. Various aspects of flip-flop circuits are described in detail to study which topology would be most suitable for ultra low supply voltage and low-power applications. Simulation results show that the power consumption decreases by at least 23% compared with other flip-flops. Also, the setup time and the hold time are improved.

Keywords

CMOS integrated circuits; flip-flops; power consumption; 65 nm CMOS technology; flip-flop circuits; power consumption; subthreshold region operation; Analytical models; CMOS technology; Circuit simulation; Circuit topology; Energy consumption; Flip-flops; Leakage current; Low voltage; Threshold voltage; Wireless sensor networks; Low-voltage; low-power; nanoscale; subthreshold;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-2952-3

Electronic_ISBN

978-1-4244-2953-0

Type

conf

DOI

10.1109/ISQED.2009.4810287

Filename

4810287