A novel ACO-based pattern generation for peak power estimation in VLSI circuits

Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue of this task is which pattern pair would cause this peak power value. An exhaustive search from all possible combinations is time-consuming and impractical for VLSI circuits with hundreds of inputs. In this paper, a new pattern generation approach with Ant Colony Optimization, which imitates the behavior of ants looking for foods, is proposed for peak power estimation. The approach returns patterns which are highly suspicious to consuming the peak power. The gate delay issue is considered in this work. Furthermore, the valid state issue in sequential circuits is considered as well. Since the real delay value is technology-dependent, these generated patterns of our approach and other approaches are then applied into a commercial power calculation tool, PrimePower, to demonstrate the effectiveness of the approach under the TSMC 0.18 mum and TSMC 0.13 mum library. The experimental results show that an average of 76% tighter lower bound for the ISCAS´85 combinational benchmarks and 52% for the ISCAS´89 sequential circuits are obtained as compared to random patterns under the TSMC 0.18 mum library. For TSMC 0.13 mum library, our patterns obtain 90% and 56% improvements over the random patterns for ISCAS´85 and ISCAS´89, respectively. As compared with the previous work, our results are also competitive.