Power aware placement for FPGAs with dual supply voltages

Usage of multiple supply voltages has raised new design challenges in IC design. We focus on the problem of power aware placement when dual supply voltages provide two high performance and low power working modes on each FPGA tile. To meet timing constrains, all logic elements within a tile need to work in the high performance mode when at least one element within that tile has tight timing requirements. To save more energy, we propose a placement flow that enables more tiles and logic elements to work in the low power mode. We start with an initial placement that provides coarse timing requirements. A heuristic algorithm is proposed to select a subset of tiles to host critical elements. Considering the candidate hosts, a set of movements are generated and those with least cost overheads are accepted. We also introduce "saving ratio" as a new metric for measuring quality of MSV-based power aware placement algorithms. Our proposed placement flow improves both the static and dynamic power consumption by about 4.5% which translates into an improvement in the saving ratio by 20.25%.