Effects of 3D via and die attach on power integrity of a packaged IC

Author

Yi-Chieh Lin ; Yu-Chih Lin ; Horng, Tzyy-Sheng ; Lih-Tyng Hwang

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan

fYear

2012

fDate

4-7 Dec. 2012

Firstpage

277

Lastpage

279

Abstract

In this paper, we first investigated the effects of 3D single and multi-via(s) on power integrity of a packaged IC. Backside vias have been an essential element in MMIC technology. This paper analyzed and characterized single and multiple backside via(s). The results of this investigation can be used as a design guideline for the now very popular Through Silicon Via (TSV) technology. We also investigated how die attach techniques (vias with silver epoxy or vias with blanket Cu) affected the distribution of return ground currents. We mainly wanted to know if silver epoxy can be adequately applied in millimeter wave frequencies. This study will offer insights to future package designs that employ Cu-to-Cu bonding technology.

Keywords

MMIC; integrated circuit packaging; microassembling; three-dimensional integrated circuits; 3D single via; Ag; Cu; Cu-to-Cu bonding technology; MMIC technology; blanket Cu; die attach; multiple backside vias; packaged integrated circuit; power integrity; return ground currents; silver epoxy; silver vias; single backside via; through silicon via; Ceramics; Copper; Electrical resistance measurement; Inductance; Integrated circuits; Microassembly; Silver; Ceramics; power integrity; through vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1330-9

Electronic_ISBN

978-1-4577-1331-6

Type

conf

DOI

10.1109/APMC.2012.6421571

Filename

6421571