Power estimation methodology for a high-level synthesis framework

As adoption of system-level hardware design is increasing in industry and academia, accurate power estimation at this level is becoming important. In this paper, we present a system-level power estimation methodology, which is based on a high-level synthesis framework and supports sufficiently accurate power estimation of hardware designs at the system-level. For early and accurate power estimation, the proposed methodology utilizes register transfer level (RTL) probabilistic power estimation technique controlled by the system-level simulation. Furthermore, our methodology does not require a designer to move to the traditional RTL power estimation methodology, thus facilitating easy and early power analysis and aiding the cause of adoption of system-level design practices in ASIC design flow. This paper provides detailed description of our methodology including tools used, algorithm for extracting activity from system-level value change dump and finally mapping this information for RTL power estimation. We show the usefulness of our approach by performing power estimation on synthesizable cycle-accurate transaction-level (CATL) design models of reasonable complexity such as prototype processor model (VeSPA processor), universal asynchronous receiver and transmitter (UART), FFT filter, etc. We demonstrate our methodology through industry standard EDA tools used in the ASIC design flow and show that the loss in accuracy for the proposed approach with respect to the state-of-the-art RTL power estimation techniques ranges from 3-9%. The speed up gained using our approach is upto 12 times more than RTL simulation based power estimation approach.