Performance measurement and improvement of asymmetric three-tr. cell (ATC) DRAM toward 0.3V memory array operation

Author

Ichihashi, Motoi ; Toda, Haruki

fYear

2006

fDate

3-7 Jan. 2006

Abstract

For a Mb-class embedded memory, asymmetric three-transistor cell (ATC) DRAM has been reported. The memory cell is a non-destructive-read type and the memory array runs at 0.5V, half the voltage of normal peripheral circuits, on a 90nm generic CMOS logic process. A sense amplifier designed for this DRAM is insensitive to input capacitance and can operate with a power supply voltage as low as 0.5V. Through our experiments, we have identified three ways to improve the ATC DRAM. And these improvements enable the sense time to be 6.3ns and refresh power consumption to be 45μW with 0.3V memory array voltage by simulation results.

Keywords

CMOS logic circuits; CMOS memory circuits; DRAM chips; amplifiers; logic design; transistor circuits; 0.3 V; 0.5 V; 45 muW; 6.3 ns; 90 nm; CMOS logic process; asymmetric three-transistor cell DRAM; embedded memory; memory array operation; memory cell; power supply voltage; sense amplifiers; CMOS logic circuits; CMOS memory circuits; CMOS process; Capacitance; Energy consumption; Logic arrays; Low voltage; Measurement; Power supplies; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-2502-4

Type

conf

DOI

10.1109/VLSID.2006.132

Filename

1581499