Decompression dual core for SoPC applications in high speed FPGA

This paper presents a dual core architecture for decompression using the deflate algorithm. The flexibility of the system-on-a-programmable-chips (SoPC) makes possible the introduction of these computationally intensive cores inside a field- programmable-gate-array (FPGA). The proposed architecture is composed of two different cores. One is in charge of the translation of the Huffman codes while the other one regenerates the decompressed data using the LZ77 algorithm. The cores can be used in conjunction or independently depending on the final structure of the SoPC.