• DocumentCode
    3096098
  • Title

    Designing-in device reliability during the development of high-performance CMOS logic technology to 0.13 μm

  • Author

    Nayak, Deepak ; Hao, Ming-Yin ; Hijab, Raif

  • Author_Institution
    Adv. Micro Devices Inc., Sunnyvale, CA, USA
  • fYear
    1997
  • fDate
    13-16 Oct 1997
  • Firstpage
    42
  • Lastpage
    44
  • Abstract
    During the development of advanced CMOS process technology, the trade-off between high performance and reliability is being made in each generation of technology. In this work, we present these trade-offs as the CMOS devices are scaled from 0.5 μm-generation to 0.13 μm-generation technology
  • Keywords
    CMOS logic circuits; integrated circuit design; integrated circuit reliability; integrated circuit testing; logic design; logic testing; 0.13 micron; 0.5 micron; CMOS device downscaling; CMOS logic technology; CMOS performance; CMOS process technology; CMOS reliability; designed-in device reliability; Boron; CMOS logic circuits; CMOS process; CMOS technology; Hot carriers; Hybrid junctions; Logic design; Logic devices; Microprocessors; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop Final Report, 1997 IEEE International
  • Conference_Location
    Lake Tahoe, CA
  • Print_ISBN
    0-7803-4205-4
  • Type

    conf

  • DOI
    10.1109/IRWS.1997.660279
  • Filename
    660279
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3096098