Research and analysis of routing algorithms for NoC

Author

Xu, Yongfeng ; Zhou, Jianyang ; Liu, Shunkui

Author_Institution

Dept. of Electron. Eng., Xiamen Univ., Xiamen, China

Volume

2

fYear

2011

fDate

11-13 March 2011

Firstpage

98

Lastpage

102

Abstract

The Network-on-Chip has been recognized as a paradigm to solve System-on-Chip (SoC) design challenges. The routing algorithm is one of key researches of a NoC design. Its importance and effect on the performance of the network is accordingly cardinal. High-performance, load-balance, deadlock-free and livelock-free, fault-tolerant are the desirable properties of a routing algorithm for NoC. In this paper, we summarize routing algorithms used for NoC by simply comparison and analysis,and give the merits and demerits of some routing algorithms.

Keywords

fault tolerance; integrated circuit design; integrated circuit reliability; network routing; network-on-chip; NoC; fault-tolerant; load-balance; routing algorithm analysis; system-on-chip design; Adaptive systems; Algorithm design and analysis; Fault tolerance; Fault tolerant systems; Routing; Switches; System recovery; Deadlock and Live lock; Network-on-Chip; fault-tolerant; routing algorithm; wormhole-switching;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Research and Development (ICCRD), 2011 3rd International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-61284-839-6

Type

conf

DOI

10.1109/ICCRD.2011.5764092

Filename

5764092