A two-level pipelined implementation of the IDEA cryptographic algorithm

Author

Salomão, Sérgio L C ; Alves, Vladimir C. ; Filho, Eliseu M C

Author_Institution

Mil. Inst. of Eng., Rio de Janeiro, Brazil

fYear

1998

fDate

30 Sep-3 Oct 1998

Firstpage

158

Lastpage

161

Abstract

Data security is an important issue in today´s computer networks. This paper presents the HiPCrypto chip, which implements the IDEA cryptographic algorithm. HiPCrypto is oriented towards computer network applications demanding high throughput. Its architecture exploits both the spatial and the temporal parallelism available in the IDEA algorithm. When operating with a 53 MHz clock, HiPCrypto can encrypt/decrypt at data rates up to 3.4 Gbps

Keywords

cryptography; pipeline processing; wide area networks; 3.4 Gbit/s; 53 MHz; HiPCrypto chip; IDEA cryptographic algorithm; computer network applications; data rates; spatial parallelism; temporal parallelism; throughput; two-level pipelined implementation; Application software; Computer applications; Computer networks; Cryptography; Data security; Military computing; Principal component analysis; Professional activities; Smart cards; Zinc;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-8186-8704-5

Type

conf

DOI

10.1109/SBCCI.1998.715431

Filename

715431

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3097717