DocumentCode
3098589
Title
Exploiting hierarchy in a cache-based switch-level simulator
Author
Jones, Larry G.
Author_Institution
Dept. of Comput. Sci., Illinois Univ., Urbana-Champaign, IL, USA
fYear
1992
fDate
16-19 Mar 1992
Firstpage
207
Lastpage
211
Abstract
The article presents a caching method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a factor of two. While caching may require additional memory it is shown how the structural hierarchy can be exploited to quickly identify subnetworks computing identical functions, merge their cache tables and significantly reduce the memory requirements
Keywords
circuit analysis computing; digital integrated circuits; dynamic programming; cache tables; cache-based switch-level simulator; structural hierarchy; subnetwork evaluation; Analytical models; Boolean functions; Circuit simulation; Computational modeling; Costs; Data structures; Databases; Digital circuits; Dynamic programming; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location
Brussels
Print_ISBN
0-8186-2645-3
Type
conf
DOI
10.1109/EDAC.1992.205924
Filename
205924
Link To Document