DocumentCode
3099182
Title
20 MS/s, 1.6 mW, 50dB SFDR switched-capacitor DAC
Author
Nizhnik, Oleg ; Higuchi, Kohei ; Maenaka, Kazusuke ; Ooshima, Takashi
Author_Institution
Maenaka Human-sensing Fusion Project, ERATO Project Group of JST, Himeji, Japan
Volume
3
fYear
2011
fDate
11-13 March 2011
Firstpage
340
Lastpage
344
Abstract
This paper presents a 1.6 mW, 20 MS/s DAC with 0.33 pJ/conversion-step figure-of-merit, effective number of bits exceeding 7.9 and 0.40 mm2 total chip area. A new variety of the non-binary series allowed design of the switched-capacitor charge pump array, with switched capacitance 7.3 pF, maximum to minimum capacitance ratio 7.2 and 7 matched capacitors, resulting in compact DAC layout. The proposed device was implemented in the 0.18 um TSMC CMOS technology.
Keywords
CMOS integrated circuits; capacitors; charge pump circuits; digital-analogue conversion; TSMC CMOS technology; capacitance 7.3 pF; compact DAC layout; matched capacitors; nonbinary series; power 1.6 mW; size 0.18 mum; switched-capacitor DAC; switched-capacitor charge pump array; CMOS integrated circuits; Capacitance; Capacitors; MIM capacitors; Power supplies; Switches; Switching circuits; Digital-analog conversion; Switched capacitor circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Research and Development (ICCRD), 2011 3rd International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-61284-839-6
Type
conf
DOI
10.1109/ICCRD.2011.5764209
Filename
5764209
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