DocumentCode
3099570
Title
An automatic layout generator for analog circuits
Author
Conway, J.D. ; Schrooten, G.G.
Author_Institution
Philips Res. Labs., Eindhoven, Netherlands
fYear
1992
fDate
16-19 Mar 1992
Firstpage
513
Lastpage
519
Abstract
A `design by example´ approach to automatic layout generation for analog circuits is presented. This approach uses a sample layout, the template, to graphically capture an expert´s knowledge of analog device placement and routing for a given module type. To generate a module, one supplies the required electrical parameters for each device and a geometrical constraint on the module´s shape e.g. a desired aspect ratio. Using exhaustive floorplan area optimisation techniques, the tool then determines the optimum shape of each device so as to satisfy the user´s geometrical constraint. Subsequently, layout is generated by transforming (via compaction) the template into a module, substituting the devices in the template by newly generated devices with the user-supplied electrical parameters and the determined geometrical shapes. This technique produces good quality layout in reasonable amount of time, by availing of the expert designer knowledge embedded in the template and by taking analog specific features like device matching and merging into account during the layout transformation phase. This approach is illustrated using an n-type super MOS transistor circuit generator
Keywords
circuit layout CAD; insulated gate field effect transistors; linear integrated circuits; analog MOS circuits; analog circuits; analog device placement; analog specific features; automatic layout generation; compaction; design by example; desired aspect ratio; device matching; exhaustive floorplan area optimisation techniques; expert designer knowledge; geometrical constraint; module type; n-type super MOS transistor circuit generator; optimum shape; routing; sample layout; template; user-supplied electrical parameters; Analog circuits; Compaction; Crosstalk; Design automation; Laboratories; Layout; MOSFETs; Merging; Routing; Shape;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location
Brussels
Print_ISBN
0-8186-2645-3
Type
conf
DOI
10.1109/EDAC.1992.205989
Filename
205989
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