DocumentCode
3099609
Title
YOR: a yield optimizing routing algorithm by minimizing critical area and vias
Author
Kuo, Sy-Yen
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
1992
fDate
16-19 Mar 1992
Firstpage
525
Lastpage
529
Abstract
The goal of a channel routing algorithm is to route the nets with as few tracks as possible to minimize the chip area and achieve 100 percent connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce the critical areas which are susceptible to defects. A new channel routing algorithm is presented to deal with this problem. The approach is to systematically eliminate critical areas by floating, burying, and bumping net segments as well as shifting vias. The yield optimizing routing (YOR) algorithm also minimizes the number of vias. The experimental results show that large reduction in the number of critical areas and significant improvement in yield are achieved
Keywords
circuit layout CAD; counting circuits; integrated circuit manufacture; minimisation; YOR; bumping; burying; channel routing algorithm; chip area; critical areas; floating; manufacturing yield; net segments; vias; yield optimizing routing; Circuit faults; Conducting materials; Costs; Integrated circuit synthesis; Integrated circuit yield; Manufacturing; Production facilities; Routing; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location
Brussels
Print_ISBN
0-8186-2645-3
Type
conf
DOI
10.1109/EDAC.1992.205991
Filename
205991
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