Improving SRAM read/write margin with asymmetric halo MOSFET

Author

Nii, Koji ; Yabuuchi, Makoto ; Fujiwara, Hidehiro ; Tsukamoto, Yasumasa ; Maekawa, Koji ; Igarashi, Motoshige

Author_Institution

Renesas Electron. Corp., Japan

fYear

2011

fDate

7-9 Dec. 2011

Firstpage

1

Lastpage

2

Abstract

We propose SRAM bitcells with asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks for halo implant steps. AH-MOS has different drain-source currents (Ids) between forward and reverse directions (Fig. 1). By implanting high and low dose for drain and source regions respectively, Ids flowing from drain to source (forward) gets larger than that from source to drain (reverse). Fig. 2 shows 6T SRAM bitcell with AH-MOS [1]. The current at pass-gate (PG), which consists of AH-MOS, flows bi-directionally in read and write mode. The pull-down (PD) is symmetric halo implant dose MOSFET (SH-MOS) due to unidirectional currents. The pull-up (PU) is also SH-MOS.

Keywords

MOSFET; SRAM chips; AH-MOS; SH-MOS; SRAM bitcells; SRAM read-write margin; asymmetric halo implant dose MOSFET; drain-source currents; drain-source regions; pass-gate current; symmetric halo implant dose MOSFET; Arrays; Implants; Logic gates; MOS devices; MOSFET circuits; Random access memory; Resists;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium (ISDRS), 2011 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4577-1755-0

Type

conf

DOI

10.1109/ISDRS.2011.6135267

Filename

6135267