Rapid clock recovery technique with monotonic phase error metric

One of the most common configurations utilized for acquiring a local timing reference is the absolute value early-late gate bit synchronizer. The primary disadvantage to this method, and most similar approaches, is that it does not exhibit a linearly increasing phase error characteristic. An unstable equilibrium exists at phase errors of ±1/2 bit which may delay synchronization. A rapid clock recovery technique is described which has an error signal which increases monotonically over a full bit interval, eliminating the unstable equilibrium point of the conventional methods. This can be a significant advantage in systems which require very high probability of synchronization with short preambles. In addition, the phase detector output can be readily tailored to match the expected filtering of the data. A practical advantage of the rapid clock recovery module presented is that the entire process (except for the one-bit quantizing) including sampling, shift register, table look-up, memory, clock generation, and clock adjustment can be performed in a single-chip microprocessor, using on-board RAM and ROM, at data rates up to several kilobits per second