Vertical-channel stacked array (VCSTAR) for 3D NAND flash memory

Author

Kim, Yoon ; Park, Se Hwan ; Kim, Wandong ; Seo, Joo Yon ; Park, Byung-Gook

Author_Institution

Inter-Univ. Semicond. Res. Center (ISRC), Seoul Nat. Univ., Seoul, South Korea

fYear

2011

fDate

7-9 Dec. 2011

Firstpage

1

Lastpage

2

Abstract

Recently, 3D stacked NAND flash architectures have been proposed to solve scaling limit of the planar NAND flash memory based on floating-gate type [1]-[2]. However, theses structures have several drawbacks. For TCAT[1], declined hole-etch slope leads to different curvature radius of each stacked active layers. Consequently, different electric field is applied to each layer in program operation, which causes the threshold voltage distribution problem. In case of VSAT[2], it is almost impossible to implement metal gate structure. Also, VSAT has the limitation of the stacking extendability due to inefficient bit line current flow (going up and down).

Keywords

NAND circuits; flash memories; 3D NAND flash memory; 3D stacked NAND flash architectures; TCAT; VCSTAR; VSAT; bit line current flow; curvature radius; declined hole-etch slope; electric field; floating-gate type; metal gate structure; planar NAND flash memory; program operation; stacked active layers; stacking extendability; threshold voltage distribution problem; vertical-channel stacked array; Arrays; Doping; Flash memory; Logic gates; Stacking; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium (ISDRS), 2011 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4577-1755-0

Type

conf

DOI

10.1109/ISDRS.2011.6135406

Filename

6135406