Thermal design optimization of a package on package

In the past decade, compact components such as Chip Scale Packages and flip chips were the work horses of miniaturization. However, emerging applications are now demanding even higher packaging density. In order to fulfill this requirement, three dimensional packaging was evolved. Advantages of three dimensional packaging structure include minimal conductor length and reduce speed limiting inter chip interconnects. In the past, this packaging approach was relegated to memory devices with relatively low power (flash). Recent focus, however, has been to extend the applications of stacked packages to include high performance memory, DRAM, logic-memory stack, system in a package etc. Stacked packages can be package-on-package or die stacked (with several dice inside the same casing) or both. It is common in a mobile phone that the stacked CSP is mounted on a circuit board and there is no space for air circulation. Depending on the power, due to the torturous heat flow path, it can result in high temperatures of the packaged die and the thermal specifications of the package can be easily exceeded. Hence there is a need for thermal simulation of a variety of packaging architecture for applications of interest. The objective of this paper was to perform thermal characterization of a commercially viable PoP. In order to model this PoP, flip chip logic die package was considered as the bottom package and two memory dice stacked package was considered as the top package. Eleven different scenarios were taken into consideration for the numerical analysis. Permutations of 0.1, 0.2, 0.3 and 1, 2 and 3 W memory die and logic die was considered respectively. Additionally two cases are also described. Steady state analysis was performed based on which guidelines were provided. For the analysis commercially available FEA tool was considered.