Efficient hardware implementation of power-line transfer functions using FPGA´s for the purpose of channel emulation

This paper presents in detail the efficient and accurate way of implementing power-line transfer functions into field programmable arrays (FPGA). First, some research is made concerning the characteristics of the PLC channels by analyzing different PLC channels of different sources. These channels will be implemented by using finite impulse response filters (FIR). An efficient way to improve the accuracy of the implementation is presented by combining FIR and infinite impulse response (IIR) filters. Different windowing functions are compared concerning their efficiency and accuracy. At the end of the paper a comparison of original versus emulated transfer functions are presented.