Delay estimation for CMOS functional cells

Author

Madsen, Jan

Author_Institution

Microelectron. Center, Tech. Univ. of Denmark, Lyngby, Denmark

fYear

1991

fDate

25-28 Feb 1991

Firstpage

101

Lastpage

105

Abstract

Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment

Keywords

CMOS integrated circuits; circuit layout CAD; delays; integrated logic circuits; CELLO; CMOS functional cells; RC tree network model; cell compiler; delay estimation; performance driven layout synthesis; silicon compiler environment; topological changes; worst case analysis; Algorithm design and analysis; Boolean functions; Circuit synthesis; Circuit topology; Delay estimation; Microelectronics; Network synthesis; Performance analysis; Semiconductor device modeling; Silicon compiler;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation. EDAC., Proceedings of the European Conference on

Conference_Location

Amsterdam

Type

conf

DOI

10.1109/EDAC.1991.206369

Filename

206369

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3105554