Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories

Author

Cheng, Kuo-Liang ; Tsai, Ming-Fu ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2001

fDate

2001

Firstpage

225

Lastpage

230

Abstract

We present two memory test algorithms for neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF). March algorithms are widely used in memory testing because of their linear time complexity and ease in built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns for testing the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multi-background March algorithms have shorter test length than previously proposed ones (68N for detecting SNPSFs and PNPSFs and 96N for detecting all NPSFs). Also, based on the proposed algorithms, linear-time BIST circuit can be implemented with low area overhead

Keywords

automatic testing; built-in self test; fault diagnosis; integrated circuit testing; integrated memory circuits; March algorithms; active NPSF; area overhead; linear-time BIST circuit; memory test algorithms; multiple data backgrounds; neighborhood pattern-sensitive fault test algorithms; passive NPSF; semiconductor memories; static NPSF; test length; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Digital systems; Fault detection; Random access memory; Semiconductor device testing; Semiconductor memory; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001

Conference_Location

Marina Del Rey, CA

Print_ISBN

0-7695-1122-8

Type

conf

DOI

10.1109/VTS.2001.923443

Filename

923443