The Design of Virtual Self-timed Block for Activity Communication in SOC

In this paper we present the architecture for virtual self-timed blocks. Being globally asynchronous locally synchronous (GALS) and lazy reactive processing units, such blocks target multi-processing on-chip systems where power consumption is an important factor. The architecture provides a hardware foundation which transparently supports the systematic organization of application-level activities (processes) and the efficient use of system resources. It further facilitates the seamless integration of IP cores into systems by enhancing the GALS paradigm and protecting clocked IP cores from the temporal nondeterminism in their environments. This work includes the basic design of the virtual self-timed block architecture, Matlab models of the important components involved, and demonstrative analyses in Matlab.