Modelling Latency-Insensitive Systems in CSP

With the advance in semiconductor technology we are able to pack more and more devices on a single chip. However, the threat comes from the long interconnect wires whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency due the long interconnects, we require the IP cores to be latency-insensitive (LI). Design and validation of LI design is studied in L.P. Cartoni, et al., (1999), L.P. Cartoni, et al.,(2001), and T. Chelcea, et al., (2004). Generalised latency-insensitive systems, design of connecting FIFOs and other communication protocols appear in T. Chelcea, et al.,(2006), S. Dasgupta, et al., (2006), D. Potop-Butucaru, et al., (2006), and M. Singh, et al., (2003). Process algebras provide a well-studied framework for modelling and verifying concurrent systems. In this work we try to address the problem of long interconnects by modelling the latency insensitive protocol in the discrete time version of CSP. Time is modelled in terms of events occurring at regular intervals, modelled by the event took.