A test and maintenance controller for a module containing testable chips

Author

Breuer, Melvin A. ; Lien, Jung-Cheun

Author_Institution

Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1988

fDate

12-14 Sep 1988

Firstpage

502

Lastpage

513

Abstract

A design of a module test and maintenance controller (MMC) is presented. Driven by structured test programs, an MMC is able to test every chip in a module via an ETM-BUS or a boundary scan bus. More than one test bus can be controlled by an MMC. MMC processor instructions, when executed, produce bus timing sequences which control a chip´s BIT structures. The proposed MMC is a universal design. The difference between MMCs on different modules is the test programs which they executed and the number of test buses they control. Performance analysis indicates that either a RISC (reduced-instruction-set computer)-type processor or DMA controller is required in the MMC. Some self-test features of the MMC are also presented

Keywords

automatic test equipment; automatic testing; controllers; integrated circuit testing; modules; protocols; DMA controller; ETM-BUS; automatic testing; boundary scan bus; bus timing sequences; maintenance controller; module test; reduced-instruction-set computer; structured test programs; testable chips; Automatic testing; Built-in self-test; Control systems; Design for testability; Monitoring; Process control; Protocols; System testing; Timing; Very high speed integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207830

Filename

207830