Evaluation of system BIST using computational performance measures

The impact of built-in self-test (BIST) techniques and system maintenance strategies on the performance of a VLSI processor system is examined. The specific BIST technique used was shown to have a significant influence upon instantaneous and cumulative system reward. It was shown that the additional overhead of the distributed and BILBO approaches is justified for this model when area utilization and cumulative area utilization are considered. For the assumed design parameters, the results presented allow a VLSI system designer to choose an optimal configuration based on system requirements and individual component parameters. The optimal performance will also depend on system and component parameters such as processor failure rates and fault coverage. These results are relevant to the design, evaluation, and optimization of highly reliable, high-performance digital processing systems