Trend of the CMOS process technology for system on a chip

Author

Nishimura, Tadashi

Author_Institution

ULSI Dev. Center, Mitsubishi Electr. Corp., Itami, Japan

fYear

2000

fDate

2000

Firstpage

20

Lastpage

24

Abstract

The coming 0.13 μm technology node will establish the SoC era, in which a chip consists of several systems rather than IPs. But the technology node contains many challenging issues. A new lithography tool with an ArF eximer laser will be required to develop flexible fine patterns. It is predicted that both high speed (high ON current) and low power (low OFF current) would be impossible to achieve on one chip with one process specification. Gate leakage current becomes the biggest challenge against the progress on the road map. Solutions may be diversified at the beginning of the 0.13 μm technology node to manage the business chips. High density pattern related ion beam shadowing is another challenge, which will affect the ion implanter specification at this technology node. The precise control of the wafer processing based on the smart integration is the key issue. SOI can provide the solutions to these key challenges

Keywords

CMOS integrated circuits; integrated circuit technology; ion implantation; leakage currents; photolithography; silicon-on-insulator; 0.13 micron; CMOS process technology; SOI; SoC era; flexible fine patterns; gate leakage current; high ON current; high density pattern related ion beam shadowing; ion implanter specification; lithography tool; low OFF current; low power; smart integration; system on chip; wafer processing control; CMOS process; CMOS technology; Dielectrics and electrical insulation; Leakage current; Lithography; Roads; Space technology; System-on-a-chip; Technology management; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Ion Implantation Technology, 2000. Conference on

Conference_Location

Alpbach

Print_ISBN

0-7803-6462-7

Type

conf

DOI

10.1109/.2000.924080

Filename

924080