DocumentCode
3112321
Title
Junction capacitance reduction by S/D junction compensation implant
Author
Curello, G. ; Rengarajan, R. ; Faul, J. ; Kieslich, A. ; Glawischnig, H.
Author_Institution
Memory Products Div., Infineon Technol. AG, Dresden, Germany
fYear
2000
fDate
2000
Firstpage
46
Lastpage
49
Abstract
Parasitic capacitances normally present in CMOS transistors are recognized as detrimental factors in overall Transistor and Circuit performance. In this report results from an investigation of a simple method to reduce Junction Capacitance (Cj) in 0.20 and 0.17 μm embedded DRAM technologies are presented. The results shown indicate that Cj of both NFETs and PFETs can be reduced (without significantly affecting other transistor parameters) by about 20%
Keywords
CMOS integrated circuits; DRAM chips; capacitance; 0.17 mum; 0.2 mum; CMOS transistors; NFETs; PFETs; S/D junction compensation implant; embedded DRAM technologies; junction capacitance reduction; parasitic capacitances; CMOS technology; Circuit optimization; Implants; Integrated circuit interconnections; Logic devices; Logic gates; Neodymium; Parasitic capacitance; Productivity; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Ion Implantation Technology, 2000. Conference on
Conference_Location
Alpbach
Print_ISBN
0-7803-6462-7
Type
conf
DOI
10.1109/.2000.924086
Filename
924086
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