Epi Defined (ED) FinFET with dynamic threshold: Reduced VT variability, enhanced performance, and a novel Multiple VT

Line Edge Roughness (LER) based V_T variability is one of the major roadblock for the scaling of FinFET to the future technology nodes. LER causes change in fin width leading to quantum confinement based V_T variability. Earlier we proposed Epitaxy Defined FinFETs (EDFinFET) in which channel depletion width is defined by highly uniform epitaxy and thus remains constant, leading to low LER based variability. In this paper, we discuss immunity of DTMOS configuration of EDFinFET against LER induced V_T variability and it is shown to be almost ideal. We also propose a novel approach to enable multiple V_T for this device to span LOP and HP technology requirements with 15% better HP performance. The performance improvement and overall V_T variability is compared to FinFETs. The above advantages combined can help DTMOS configuration of EDFinFET to operate at low power and hence be a viable option for sustainable scaling to future CMOS technology nodes.