Testing of programmable logic devices (PLD) with faulty resources

Author

Ashen, D.G. ; Meyer, F.J. ; Park, N. ; Lombardi, F.

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

1997

fDate

20-22 Oct 1997

Firstpage

76

Lastpage

84

Abstract

This paper presents a combined approach for testing logic and routing resources in programmable logic devices (PLDs). The proposed approach is based on configuring the PLD using different arrangements such as built-in self-test schemes (for example, a parity chain) and one-dimensional arrays (with and without common inputs). It is proved that the proposed approach achieves 100% fault coverage under a fault model consisting of a single fault in the logic resources and active routing devices, or multiple faults in the interconnection channels and input/output lines

Keywords

automatic testing; built-in self test; fault diagnosis; integrated circuit interconnections; logic arrays; logic testing; network routing; programmable logic devices; active routing devices; built-in self-test schemes; fault coverage; fault model; faulty resources; input/output lines; interconnection channels; logic testing; multiple faults; one-dimensional arrays; parity chain; programmable logic devices; routing resources; Built-in self-test; Field programmable gate arrays; Legged locomotion; Logic arrays; Logic devices; Logic testing; Programmable logic arrays; Programmable logic devices; Routing; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on

Conference_Location

Paris

ISSN

1550-5774

Print_ISBN

0-8186-8168-3

Type

conf

DOI

10.1109/DFTVS.1997.628312

Filename

628312