A test vehicle for monitoring and improvement of CMOS reliability performance

Author

Remmerie, G.

Author_Institution

Mietec Alcatel, Oudenaarde, Belgium

fYear

1990

fDate

29 May-1 Jun 1990

Firstpage

444

Lastpage

448

Abstract

Monitoring reliability performance through accelerated testing on products is at least incomplete and failure analysis is difficult. Device level reliability stress tests are an attractive complement, and offer a wider range of overstresses, a clearer relationship between stress and failure, and reduced stress times. A 2.0 micron CMOS testchip has been built, containing stress patterns for interconnect, dielectrics, diffusions and transistors. A set of stress conditions has been designed, and data handling software has been developed to analyse parameter shifts due to ageing and assembly. The system is used for monitoring and for evaluation of process changes

Keywords

CMOS integrated circuits; ageing; automatic testing; circuit reliability; failure analysis; integrated circuit testing; 2.0 micron; CMOS; accelerated testing; data handling software; dielectrics; failure analysis; interconnect; monitoring; overstresses; parameter shifts; reliability performance; stress tests; stress times; test vehicle; Aging; Assembly; Condition monitoring; Data handling; Dielectrics; Failure analysis; Life estimation; Stress; Testing; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '90

Conference_Location

Paris

Print_ISBN

0-8186-2066-8

Type

conf

DOI

10.1109/EASIC.1990.207986

Filename

207986