FPGA Based Implementation of Power Optimization of 32 Bit RISC Core Using DLX Architecture

The aim of the work is to design and reduce the power consumption of low power 32 bits RISC core processor. The design is based on 5-stage pipelined DLX architecture. This paper proposes the design for the low power RISC processor. The DLX architecture with pipelined control in a RISC core consists of Fetch, Decode, Execute, Pipeline Control and Memory. The reduction in the power is achieved using HDL modification technique. Leakage power i.e Quiescent power which is also a static power in the processor cannot be reduced. Algorithm modification in the execute block of the RISC core will reduce the power consumed by the processor. 13.33% is the total power reduction between a normal processor and the low power version of the processor.