EMC macro-modeling of CMOS inverter using LECCS-I/O model with additional current source

The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.