On-line error detection for finite field multipliers

In this paper error-detection is applied to finite field multipliers. It is shown that by using parity prediction, error-detection can be incorporated into these multipliers with very low hardware overheads. The structures of error-detection circuits for any finite field are given for these multipliers. The hardware overheads of these methods are independent of m and so for large values of m the presented approaches are particularly hardware efficient. The fault coverage of these structures are investigated by simulation experiments