• DocumentCode
    3116065
  • Title

    Using target faults to achieve a minimized partial scan path

  • Author

    Gundlach, H.H.S. ; Koch, B. ; Müller-Glaser, K.D.

  • Author_Institution
    Inst. for Comput. Aided Circuit Design, Erlangen-Nurnberg Univ., Germany
  • fYear
    1991
  • fDate
    15-17 April 1991
  • Firstpage
    4
  • Lastpage
    9
  • Abstract
    Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible. Also the combination of the structural selection and the selection with respect to target faults is proposed. First results prove its effectiveness.<>
  • Keywords
    VLSI; automatic testing; fault location; integrated circuit testing; DFT-strategy; minimized partial scan path; sequential ATPG-benchmarks; structural selection; target faults; Algorithm design and analysis; Automatic test pattern generation; Circuit faults; Circuit synthesis; Circuit testing; Design for testability; Electrical fault detection; Fault detection; Feedback loop; Integrated circuit measurements;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
  • Conference_Location
    Atlantic City, NJ, USA
  • Type

    conf

  • DOI
    10.1109/VTEST.1991.208124
  • Filename
    208124