DocumentCode
3116273
Title
A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG
Author
Moriyasu, Takanori ; Ohtake, Satoshi
Author_Institution
Grad. Sch. of Eng., Oita Univ., Oita, Japan
fYear
2013
fDate
3-5 July 2013
Firstpage
755
Lastpage
759
Abstract
This paper proposes a method of LFSR seed generation for scan-based BIST of VLSI circuits. The proposed method targets static faults and utilizes a commercial ATPG tool. Experimental results show that the proposed method can improve fault coverage and reduce the number of seeds compared with the conventional seed generation.
Keywords
VLSI; automatic test pattern generation; boundary scan testing; built-in self test; shift registers; LFSR seed generation; VLSI circuits; commercial ATPG tool; constrained ATPG; fault coverage; scan-based BIST; static faults; Automatic test pattern generation; Benchmark testing; Built-in self-test; Circuit faults; Integrated circuit modeling; Very large scale integration; constrained ATPG; reseeding of LFSR; scan-based BIST; seed generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Complex, Intelligent, and Software Intensive Systems (CISIS), 2013 Seventh International Conference on
Conference_Location
Taichung
Print_ISBN
978-0-7695-4992-7
Type
conf
DOI
10.1109/CISIS.2013.136
Filename
6603986
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