DocumentCode
3116944
Title
Delay testing and failure analysis of ECL logic with embedded memories
Author
Welch, Kyle G. ; Monzel, James A. ; Kent, Donald S. ; Joseph, Thomas W.
Author_Institution
IBM, East Fishkill, Hopewell Junction, NY, USA
fYear
1991
fDate
15-17 April 1991
Firstpage
254
Lastpage
259
Abstract
Two delay testing techniques, ´weighted random pattern´ (WRP) test for logic and ´algorithmic pattern generation at the tester´ (APG @ TT) for embedded memories are discussed. Several performance fails detected with these test techniques, escaping prior tests, are presented and potential failure modes predicted. AC probing techniques used to replicate the fails during failure analysis are featured.<>
Keywords
circuit reliability; delays; emitter-coupled logic; failure analysis; integrated circuit testing; integrated logic circuits; integrated memory circuits; logic testing; AC probing techniques; ECL logic; algorithmic pattern generation; delay testing techniques; embedded memories; failure analysis; failure modes; performance fails; weighted random pattern; Automatic testing; Delay; Failure analysis; Fault detection; Feedback; Logic testing; Performance evaluation; Registers; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location
Atlantic City, NJ, USA
Type
conf
DOI
10.1109/VTEST.1991.208167
Filename
208167
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