• DocumentCode
    3117136
  • Title

    Efficient maximal convex custom instruction enumeration for extensible processors

  • Author

    Xiao, Chenglong ; Casseau, Emmanuel

  • Author_Institution
    Irisa, Univ. of Rennes I, Lannion, France
  • fYear
    2011
  • fDate
    2-4 Nov. 2011
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instructions that can be implemented in special hardware units make it possible to improve performance and decrease power consumption in extensible processors. The key issue involved is to generate and select automatically the custom instructions from a high-level application code. However, enumerating all possible custom instructions of a given dataflow graph is a computationally difficult problem. In this paper, we propose an efficient algorithm for the exact enumeration of maximal convex custom instructions. The state of the art algorithms use either a bottom-up manner or a top-down manner to solve the problem. The proposed algorithm enumerates all maximal convex custom instructions by using a sandwich manner that combines the advantage of the bottom-up manner and the top-down manner. Compared to the latest algorithm, our algorithm can achieve orders of magnitude speedup.
  • Keywords
    data flow graphs; instruction sets; multiprocessing systems; base instruction set; bottom-up manner; custom instructions; dataflow graph; extensible processor; general-purpose processor; high-level application code; maximal convex custom instruction enumeration; performance improvement; power consumption; sandwich manner; top-down manner; Binary search trees; Clustering algorithms; Hardware; Heuristic algorithms; Program processors; Registers; Runtime; ASIPs; Extensible processors; custom instruction generation algorithm; maximal convex custom instruction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on
  • Conference_Location
    Tampere
  • Print_ISBN
    978-1-4577-0620-2
  • Electronic_ISBN
    978-1-4577-0619-6
  • Type

    conf

  • DOI
    10.1109/DASIP.2011.6136868
  • Filename
    6136868